This section endeavors to supply a context or background for the various exemplary embodiments of the invention as recited in the claims. The content herein may comprise subject matter that could be utilized, but not necessarily matter that has been previously utilized, described or considered. Unless indicated otherwise, the content described herein is not considered prior art, and should not be considered as admitted prior art by inclusion in this section.
It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area increases. Throughout the semiconductor industry, there is a strong drive to reduce the dielectric constant (k) of the interlayer dielectric (ILD) materials such as those existing between metal lines, for example. As a result of such reduction, interconnect signals travel faster through conductors due to a concomitant reduction in resistance-capacitance (RC) delays.
Porous ultra low-k (ULK) dielectrics have enabled capacitance reduction in advanced silicon complementary metal-oxide semiconductor (CMOS) back end of line (BEOL) structures. However, the high levels of porosity required (e.g., to achieve k values of 2.4 and lower) create issue in terms of dielectric material damage or loss due to plasma exposures (e.g., reactive ion etch (RIE), strip, dielectric barrier etch) and wet cleans (e.g., post RIE dilute hydrofluoric acid (DHF) cleans). Additionally, penetration of metals used in the liner layer (e.g., Ta, TaN) or the seed layer (e.g., Cu, Ru) into the pores of the dielectric can occur when porosity is high and the material is characterized by a high degree of pore connectivity. This leads to degradation of the dielectric break down strength and degradation of the leakage characteristics of the dielectric. All of these issues collectively may cause reliability and performance degradation in BEOL structures made using highly porous ULK dielectrics.
Although the design of a low-k dielectric material with desirable properties for implementation is demanding enough, the complexity of modern semiconductor manufacturing processes adds further complications. Some of these are a direct result from trying to utilize SiO2-based processes with porous, low-k dielectric materials that are considerably less forgiving. In this regard, adding porosity may not result in redeeming values (e.g., improved characteristics) other than lowering the dielectric constant. Critical damage to the low dielectric porous material can occur at different stages of the integration process, including: hard-mask deposition, reactive ion etch, photoresist strip, liner deposition, chemical mechanical polishing, and cap deposition, as non-limiting examples.